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B.5. SYSTEM VERILOG INTERFACE

Table B.2: cti and bte signal values

Signal group Value Description

cti 000 Classic cycle

001 Constant address burst cycle

010 Incrementing burst cycle

011-110 Reserved

111 End of burst

bte 00 Linear burst

01 4-beat wrap burst

10 8-beat wrap burst

11 16-beat wrap burst

CLK_I

ACK_I

STB_O

CYC_O

SEL_O

WE_O

DAT_I

DAT_O

ADR_O

CTI_O

BTE_O

Master signals

VALID VALID VALID VALID

VALID

n+4 n+8 n+C

010 111

Figure B.5: Wishbone linear increment burst.

signals the end of the burst by setting the cti signal to 111.

The slave will not get a new address until the last transfer is completed as is obvious from

the ﬁgure. This means that the slave will have to generate the following addresses internally

according to the cti and bte signals. In the case of a linear increment this implies that the

slave must contain a counter that increments the address.

B.5 System Verilog Interface

This is the System Verilog interface declaration used in the lab course.

Listing B.1: System Verilog Interface for the Wishbone bus

i n t e r f a c e w i s h b on e ( i np ut l o g i c c l k , r s t ) ;

t y p e d e f l o g i c [ 3 1 : 0 ] a d r _ t ;

t y p e d e f l o g i c [ 3 1 : 0 ] d a t _ t ;

a d r _ t a d r ; / / a d d r e s s b u s

d a t _ t d a t _ o ; / / w r i t e d a t a bu s

1 2 ... 74 75 76 77 78 79 80 81 82

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Cypress DCT-1D Guía de usuario Pagina 79