Cypress DCT-1D Guía de usuario descargar pdf (Pagina 58)

CHAPTER 5. LAB TASK 3

It is important to note that the DCT accelerator should still work as before if DMA

is not in use. But you are (of course) allowed to assume that the accelerator will be used

either in DMA mode or regular mode at one time. This means that the results when

both the DMA module and a wishbone master tries to write to inmem in jpeg_top at

the same time are allowed to be undeﬁned.

You should mainly modify jpeg_dma.sv in this lab but you will also have to mod-

ify jpeg_top.sv to account for the dma_bram_ signals. In jpeg_dma.sv some code

already exists, for example, an address generator capable of generating the addresses

required to read in the frame in 8×8 blocks is already instantiated. The writing and

reading of control registers and status registers are also complete. Your main task is to

complete the ﬁnite state machine.

In order to simplify debugging of your DMA accelerator it is useful to make sure

that you can change the DMA accelerator state to IDLE by writing to a control register

in the accelerator. This means that you don’t have to reset your system if jpegtest

aborts in the middle of a frame.

Preparation task 10

Complete as much as possible of the FSM in Figure 5.1 by ﬁlling in the conditions

for the state transitions. (Hint: The lab skeleton already has code for some of the state

transitions.)

Laboration task 10

Modify the DCT accelerator in lab 2 to use DMA.

Laboration task 11

Test your DCT accelerator in modelsim by modifying the monitor to

use your accelerator. Some initial code is available in

dma_dct_hw()

hw/monitor/firmware/src/dct2.c

5.1.3 How to use DMA in jpegfiles

You will have to make a few changes to jpegfiles in this lab. You should modify

both jdct.c and jcdctmgr.c so that no values are copied from memory to your

DCT accelerator. You should also note that there is a level conversion of the indata in

jcdctmgr.c, that is the pixels are modiﬁed by subtracting 128 from them. You will

have to take this into account by modifying your hardware.

5.1.4 Cache coherency issue

Normally, once DMA is involved in a system it is very important to take cache co-

herency issues into account. Especially if the processor has no bus snooping facility

to update the caches automatically. However, s ince the OR1200 has write through

caches and the DMA accelerator only reads from memory we will not have any cache

coherency issues.

Laboration task 12

Modify

jpegfiles

to use the DMA enabled DCT accelerator.

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