Cypress DCT-1D Guía de usuario descargar pdf (Pagina 63)

6.3. PROPOSED ARCHITECTURE

tions in software. We will add a new group of special purpose registers to the pro-

cessor, therefore we must make some changes in the

or1200_sprs

module. In the ﬁle

or1200_sprs.sv you will ﬁnd a

‘ifdef OR1200_SBIT_IMPL

preprocessor directive.

Add the missing code inside this directive. Once this is done you should be able to use

the special purpose registers since they have already been implemented for you.

6.2.3 Adding the Required Hardware

Finally you must add the hardware using your instruction. The main part of the work

is to extend the load and store unit described in the

or1200_lsu

module. In the ﬁle

or1200_lsu.sv you will ﬁnd a number of

‘ifdef OR1200_SBIT_IMPL

preprocessor

directives. Inside some of these you will ﬁnd a comment asking you to write some code

there. Find these places and add the missing code. In addition to this you will ﬁnd the

or1200_vlx_top

module instantiated. This is the top module for the hardware handling

the stream writing. The code for this module can be found in the or1200_vlx_top.sv

ﬁle. Further instructions on how this module should be implemented can be found in

section 6.3 and section 6.4.

6.3 Proposed Architecture

We propose the general architecture shown in ﬁgure 6.1. Gray arrows represent control

signals and black arrows represent data.

CONTROL OUT

DATA OUT

ADDRESS OUT

CODE

SIZE

CONTROL

DATA PATH

STORE

UNIT

Figure 6.1: Proposed architecture for the set bit instruction.

6.3.1 Control Unit

The control unit should be deﬁned in the

or1200_vlx_ctrl

module, a stub can be found

in ﬁle or1200_vlx_ctrl.sv. The control unit’s purpose is, as it sounds, to control

the other units. This unit might include a simple FSM or this unit might not even be

needed. All depending on your design.

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