Cypress CY62158EV30 Manual de usuario Pagina 66
- Pagina / 81
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Document Number: Rev
SheetDate: of
8/21/2009
12
B
Designer:
Drawn by:
Approved:
Drawing Title:
Page Title:
Size
Arnaldo Cruz
Arnaldo Cruz
*
0001
FPGA board for DK-EPI
EPI, LCD, Camera I/F
B
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
TI AEC - Austin
Revision History
Revision
A 6/24/2009
Released for manufacturing.
Date Description
PG0/EPI13
PG1/EPI14
PH7/EPI27
PJ0/EPI16
PD3/EPI21
PD2/EPI20
PJ6/EPI30
PJ5/EPI29
PJ4/EPI28
PJ3/EPI19
PE3/EPI25
PE2/EPI24
PB4/EPI23
PB5/EPI22
PJ1/EPI17
PH0/EPI6
PH1/EPI7
PH2/EPI1
PH3/EPI0
PH4/EPI10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2526
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J1
DF12A-50DS
PC4/EPI2
PC5/EPI3
PC6/EPI4
PC7/EPI5
PG7/EPI31
PJ2/EPI18
PF5/EPI15
PF4/EPI12
PE1/EPI9
PE0/EPI8
PH5/EPI11
PH6/EPI26
EPI8
EPI9
EPI11
EPI12
EPI13
EPI14
EPI15
EPI16
EPI17
EPI18
EPI19
EPI20
EPI21
EPI22
EPI23
EPI24
EPI25
EPI26
EPI0
EPI1
EPI2
EPI3
EPI4
EPI5
EPI6
EPI7
EPI27
R1 2.80k
3.3V
R2 2.80k
I2CSCL
I2CSDA
EPI I/F
EPI[31..0]
BANK 0
IO_L10N_0/HSWAP
143
IO_L10P_0
142
IO_L09N_0
140
IO_L09P_0
139
IO_L08N_0/VREF_0
135
IO_L08P_0
134
IO
132
IO_L07N_0/GCLK11
131
IO_L07P_0/GCLK10
130
IO_L05N_0/GCLK7
126
IO_L05P_0/GCLK6
125
IO/VREF_0
124
IO_L04N_0/GCLK5
123
IO_L04P_0/GCLK4
122
IO_L02N_0
117
IO_L02P_0
116
IO_L01N_0
113
IO_L01P_0
112
U1A
XC3S100E-4TQG144C
BANK 1
IO_L10N_1/LDC2
106
IO_L10P_1/LDC1
105
IO_L09N_1/LDC0
104
IO_L09P_1/HDC
103
IO/A0
98
IO_L08N_1/A1
97
IO_L08P_1/A2
96
IO_L07N_1/A3/RHCLK7
94
IO_L07P_1/A4/RHCLK6
93
IO_L06N_1/A5/RHCLK5
92
IO_L06P_1/A6/RHCLK4/IRDY1
91
IO_L05N_1/A7/RHCLK3/TRDY1
88
IO_L05P_1/A8/RHCLK2
87
IO_L04N_1/A9/RHCLK1
86
IO_L04P_1/A10/RHCLK0
85
IO/VREF_1
83
IO_L03N_1/A11
82
IO_L03P_1/A12
81
IO_L02N_1/A13
77
IO_L02P_1/A14
76
IO_L01N_1/A15
75
IO_L01P_1/A16
74
U1B
XC3S100E-4TQG144C
IP
141
IP
111
IP
114
IP_L03P_0
119
IP_L03N_0
120
IP_L06P_0/GCLK8
128
IP_L06N_0/GCLK9
129
IP
136
IP
78
IP
84
IP
89
IP
101
IP
107
IP/VREF_1
95
IP
38
IP
41
IP_L03P_2
47
IP_L03N_2/VREF_2
48
IP_L06P_2/RDWR_B/GCLK0
56
IP_L06N_2/M2/GCLK1
57
IP
69
IP
6
IP/VREF_3
12
IP
18
IP
24
IP
36
IP/VREF_2
66
IP/VREF_3
31
U1E
XC3S100E-4TQG144C
EPI10
EPI28
EPI29
EPI30
EPI31
EPI13
EPI14
EPI16
EPI17
EPI19
EPI20
EPI21
EPI22
EPI23
EPI24
EPI25
EPI0
EPI1
EPI6
EPI7
EPI27
EPI10
EPI28
EPI29
EPI30
EPI8
EPI9
EPI11
EPI12
EPI15
EPI18
EPI26
EPI2
EPI3
EPI4
EPI5
EPI31
HREF
VSYNC
PXLCLK
PWDN
XVCLK
I2CSCL
I2CSDA
DVP0
DVP1
DVP[7..0]
2.8VD
SIOD
SIOC
XVCLKR
L_WRn
L_XN
L_YN
L_D4
L_D1
L_D0
L_D3
L_D6
L_D7
L_D2
L_D5
L_RSTn
L_YP
L_XP
L_BLQ
LCD I/F
L_DC
L_BL
L_YN
L_XN
L_D0
L_D1
L_D2
L_D3
L_D4
L_D5
L_D6
L_D7
L_RSTn
L_RDn
L_DC
L_RDn
L_WRn
BANK 2
IO_L10N_2/CCLK
71
IO_L10P_2/VS0/A17
70
IO_L09N_2/VS1/A18
68
IO_L09P_2/VS2/A19
67
IO_L08N_2/DIN/D0
63
IO_L08P_2/M0
62
IO/M1
60
IO_L07N_2/D1/GCLK3
59
IO_L07P_2/D2/GCLK2
58
IO_L05N_2/D3/GCLK15
54
IO_L05P_2/D4/GCLK14
53
IO/D5
52
IO_L04N_2/D6/GCLK13
51
IO_L04P_2/D7/GCLK12
50
IO_L02N_2/MOSI/CSI_B
44
IO_L02P_2/DOUT/BUSY
43
IO_L01N_2/INIT_B
40
IO_L01P_2/CSO_B
39
U1C
XC3S100E-4TQG144C
X_CCLK
X_INIT_B
X_DAT
L_D0
L_D1
L_D2
L_D3
L_D4
L_D5
L_D6
L_D7
L_XN
L_YN
L_RSTn
L_RDn
L_DC
L_WRn
R21
10K
3.3V
OE
1
GND
2
VDD
4
OUT
3
U8
24.000MHz
R23
10K
3.3V
3.3V
C48
0.1uF
CLK24M
3.3V2.8VD
3.3V
C24
0.1uF
C23
0.1uF
R19
2.80k
R20
2.80k
2.8VD
5V
R6 1.0K
R4 1.0K
R5 1.0K
SCL1
3
SDA1
4
GND
1
VREF1L
2
EN
8
VREF2H
7
SCL2
6
SDA2
5
U7
PCA9306
R3
10
3.3V
3.3V
PXLCLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
J2
SMT Socket 2x17
1
2 3
Q3
MMBT3904
L_BL
R24 2.80k
PWDNR
3.3V
C49
0.1uF
A0
1
A1
2
A2
3
SDA
5
GND
4
SCL
6
WP
7
VCC
8
1K - 128X8
U9
CAT24C01
Changed camera connector P1 to vertical connector.
8/19/2009B
1B
3
2B
6
1A
2
2A
5
1OE
1
2OE
7
GND
4
VCC
8
U10
SN74CB3T3306
C50
0.1uF
2.8VD
XVCLKR
PWDNR
1
M4
4
6
8
10
12
14
16
18
20
22
24
2
3
5
7
9
11
13
15
17
19
21
23
M3
M2 M1
P1
FPC_Socket_24pin
2.8VA
DVP2
DVP3
DVP4
DVP5
DVP6
DVP7
HREF
VSYNC
DVP7
DVP6
DVP5
DVP4
DVP0
DVP3
DVP1
DVP2
TP4
TP5
TP6
TP7
TP8
Board width increased by 110mils. Added test pads.
TP4
TP5
TP6
TP7
TP8
Released for manufacturing.
100 Mil Mask
FID3
40 Mil Pad
100 Mil Mask
FID1
40 Mil Pad
100 Mil Mask
FID2
40 Mil Pad
Fiducials
100 Mil Mask
FID6
40 Mil Pad
100 Mil Mask
FID4
40 Mil Pad
100 Mil Mask
FID5
40 Mil Pad
Top
Bottom
R22
330
EPI, LCD, Camera I/F
- User’s Manual 1
- Copyright 2
- Table of Contents 3
- 4 September 5, 2010 4
- List of Figures 5
- List of Tables 6
- CHAPTER 1 7
- 8 September 5, 2010 8
- September 5, 2010 9 9
- Development Kit Contents 10
- Block Diagram 11
- 12 September 5, 2010 12
- Hardware Description 13
- CHAPTER 2 13
- Clocking 14
- Power Supplies 15
- Debugging 16
- Color QVGA LCD Touch Panel 17
- Control Interface 18
- Backlight 18
- Resistive Touch Panel 18
- User Switch and LED 19
- 20 September 5, 2010 20
- Peripheral Interface (EPI) 21
- CHAPTER 3 21
- 22 September 5, 2010 22
- CHAPTER 4 23
- 24 September 5, 2010 24
- Schematics 25
- APPENDIX A 25
- Schematic page 1 26
- Schematic page 2 27
- Schematic page 3 28
- Schematic page 4 29
- SDRAM Expansion Board 30
- EPI Signal Breakout Board 30
- Schematic page 6 31
- 32 September 5, 2010 32
- Component Locations 33
- APPENDIX B 33
- 34 September 5, 2010 34
- Center Positive (+) 35
- 36 September 5, 2010 36
- APPENDIX D 37
- 40 September 5, 2010 40
- Expansion Board 41
- APPENDIX E 41
- 42 September 5, 2010 42
- Remove board 42
- Remove jumpers 42
- 44 September 5, 2010 44
- Memory Map 45
- Flash, SRAM 47
- LCD Interface 48
- LCD_DECODE CPLD 48
- APPENDIX F 49
- Installation 50
- Using the Widget Interface 53
- Register Descriptions 55
- System Control Register 56
- Interrupt Enable Register 57
- Interrupt Status Register 57
- Memory Page Register 58
- Test PadRegister 58
- LCD Control Register 58
- 60 September 5, 2010 60
- Memory Port Register 61
- Memory Window Register 61
- Installing the Software 62
- Modifying the Default Image 62
- Default FPGA Image Blocks 62
- EPI Signal Descriptions 63
- EPI, LCD, Camera I/F 66
- SRAM, Power, JTAG 67
- Tactile Switch 67
- 68 September 5, 2010 68
- APPENDIX G 69
- Male EPI expansion connector 71
- Bottom side of EM2 module 71
- 72 September 5, 2010 72
- EM2 Expansion Board 78
- References 79
- APPENDIX H 79
- 80 September 5, 2010 80
- IMPORTANT NOTICE 81
Relacionado con productos y manuales para Los componentes del chasis Cypress CY62158EV30
(51 paginas)© 2020, manymanuals.es. Todos los derechos reservados | 0.037 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales