
Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010 59
Bit Name Description
XN LCD panel touchscreen X control. When set to 0, the LCD Xn signal is set to 0.
When set to 1, the LCD Xn signal is tri-stated.
YN LCD panel touchscreen Y control. When set to 0, the LCD Yn signal is set to 0.
When set to 1, the LCD Yn signal is tri-stated.
RST
LCD panel reset control. When set to 0, the LCD RSTn signal is set to 0. When
set to 1 the LCD RSTn signal is set to 1.
BL LCD backlight control. When set to 0, the LCD panel backlight is turned off. When
set to 1, the LCD panel backlight is turned on.
Chroma Key Register
The CHRMKEY register contains the RGB values to compare for graphics overlay operation.
During LCD screen updates, data from graphics memory is compared with this register, if a match
occurs, the corrsponding frame video pixel is sent to the output instead.
Video Capture Row Match Register
During video capture, at the start of a row, the current row value is compared with the VCRM
register. A match generates an interrupt if enabled.
Video Memory Address Low Register
The VML register provides a pointer to the start of video capture memory and contains the lower
16-bits of the address.
Video Memory Address High Register
The VMH register provides a pointer to the start of video capture memory and contains the higher 16-bits
of the address.
Video Memory Stride Register
The VMS register specifies the number of locations in video memory between successive array
elements (stride) and is measured in bytes. Using stride enables better processing time.
LCD Row Match Register
During LCD display DMA output, at the start of each row, the current row value is compared with
the LRM register. A match generates an interrupt if enabled.
Table F-7. LCD Control Register
LCDCTRL: 0xA000.0012
15 14 13 12 11 10 9 8
00000000
R R R R R R R R
76543210
0BLRST
YN XN
R R R R R/2 R/W R/W R/W
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