Cypress CY62158EV30 Manual de usuario descargar pdf (Pagina 62)

62 September 5, 2010

Installing the Software

To install the software, do the following:

1. Plug the provided cable into J4 (on the right side of the board), taking care to ensure proper

alignment and orientation. The silk-screened signal names should match, with the exception

that 2.5 V corresponds to VDD. When correctly aligned, the “JTAG-SPI Full Speed" text should

face in toward the FPGA.

Modifying the Default Image

This section provides the descriptions for the default FPGA image blocks.

Default FPGA Image Blocks

Configuration Registers

The configuration registers are transparently mapped into the Stellaris microcontroller's memory,

and are used to control the flow of the video streams. “Register Descriptions” on page 55 provides

the detailed register maps. This is contained within the vregs.v file.

Memory Windower

The memory windower allows the Stellaris microcontroller to work with a rectangular portion of a

frame buffer. For example, this can be used to pull macro-cells for JPEG compression. This is

contained within the mport.v file.

Memory Arbiter

The memory arbiter negotiates access to the external SRAM. The camera capture block is given

highest priority. This is contained within the arb.v file.

Video Compositor

The video compositor assembles the final image from the video and graphics frame buffers, and

passes it directly to the LCD Interface. It also converts the camera's VGA resolution to the LCD's

QVGA resolution by either downsampling. This is contained within the vlcd.v file.

LCD I/F

The LCD interface connects to the Kitronix 3.5" LCD display using an 8-bit parallel mode. This is

usually driven by the Video Compositor, but can also be driven directly by the EPI interface. This is

contained within the vregs.v file.

Camera I/F

The camera interface block captures pixel data from the Omnivision OV7690's 8-bit digital video

port and synchronization signals. This is contained within vcapture.v

Camera FIFO

The Camera FIFO serves two main purposes: reclocking and flow control. The camera and

camera interface run in their own 12-/24-MHz clock domain, whereas the rest of the system runs

off of the EPI clock or twice the EPI clock. The FIFO bridges these difference clock domains. The

camera does not support any flow control functions; once triggered, it proceeds through an entire

image. In order to prevent loss of pixels, this FIFO is 64 elements deep. This is contained within

the vcapture.v and async_fifo_64.v files.

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Cypress CY62158EV30 Manual de usuario Pagina 62