9-Mbit QDR- II™ SRAM 2-WordBurst ArchitectureCY7C1292DV18CY7C1294DV18Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 10 of 23IDCODEThe IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded int

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 11 of 23 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edg

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 12 of 23 TAP Controller Block Diagram0012..293031Boundary Scan RegisterIdentification Reg

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 13 of 23 TAP AC Switching Characteristics Over the Operating Range[13, 14]Parameter Descr

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 14 of 23Identification Register DefinitionsInstruction FieldValueDescriptionCY7C1292DV18 C

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 15 of 23Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R 27

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 16 of 23Power-Up Sequence in QDR-II SRAM[16]QDR-II SRAMs must be powered up and initialize

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 17 of 23Maximum Ratings(Above which the useful life may be impaired.)Storage Temperature

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 18 of 23Note: 22. Unless otherwise noted, test conditions assume signal transition time of

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 19 of 23 Switching Characteristics Over the Operating Range[22, 23]CypressParameterConsort

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 2 of 23Logic Block Diagram (CY7C1292DV18)CLKA(17:0)Gen.KKControlLogicAddressRegisterD[17:0

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 20 of 23 Switching Waveforms[27, 28, 29]Read/Write/Deselect SequenceNotes: 27. Q00 refers

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 21 of 23Ordering InformationNot all of the speed, package and temperature ranges are avail

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 22 of 23© Cypress Semiconductor Corporation, 2006. The information contained herein is sub

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 23 of 23Document History PageDocument Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRA

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 3 of 23 Pin Configurations CY7C1292DV18 (512K x 18) 234 5671ABCDEFGHJKLMNPRACQNCNCNCNCDOFF

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 4 of 23Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-SynchronousData input signa

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 5 of 23Functional OverviewThe CY7C1292DV18 and CY7C1294DV18 are synchronouspipelined Burst

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 6 of 23Byte Write OperationsByte Write operations are supported by the CY7C1292DV18.A Writ

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 7 of 23Application Example[1]Truth Table[2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQWrite

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 8 of 23Write Cycle Descriptions (CY7C1294DV18) [2, 8]BWS0BWS1BWS2BWS3KK CommentsL L L L L-

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 9 of 23IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary sc