Cypress CY7C1143V18 Manual de usuario descargar pdf

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06583 Rev. *D Revised March 06, 2008

Features

■ Separate Independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz to 375 MHz clock for high bandwidth

■ 4-Word Burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate Port Selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1141V18 – 2M x 8

CY7C1156V18 – 2M x 9

CY7C1143V18 – 1M x 18

CY7C1145V18 – 512K x 36

Functional Description

The CY7C1141V18, CY7C1156V18, CY7C1143V18, and

CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus required with common IO devices. Access to each

port is accomplished through a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR-II+ read

and write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words

(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K

, memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each port.

Port Selects enable each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 375 333 300 MHz

Maximum Operating Current 1020 920 850 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 27 28

Indice de contenidos

Pagina 1 - CY7C1143V18, CY7C1145V18

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V1818-Mbit QDR™-II+ SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency)Cypress Semiconductor Corpora

Pagina 2

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 10 of 28Application ExampleFigure 1 shows the four QDR-II+ us

Pagina 3

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 11 of 28Write Cycle Descriptions The write cycle descriptions

Pagina 4

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 12 of 28The write cycle descriptions of CY7C1145V18 follows.[

Pagina 5

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 13 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs in

Pagina 6

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 14 of 28IDCODEThe IDCODE instruction causes a vendor-specific

Pagina 7

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 15 of 28TAP Controller State DiagramFigure 2. Tap Controller

Pagina 8

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 16 of 28TAP Controller Block DiagramFigure 3. Tap Controller

Pagina 9

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 17 of 28TAP AC Switching CharacteristicsThe Tap AC Switching

Pagina 10

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 18 of 28Identification Register Definitions Instruction Field

Pagina 11

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 19 of 28Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit #

Pagina 12

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 2 of 28Logic Block Diagram (CY7C1141V18)Logic Block Diagram (

Pagina 13

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 20 of 28Power Up Sequence in QDR-II+ SRAMDuring Power Up, whe

Pagina 14

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 21 of 28Maximum RatingsExceeding maximum ratings may shorten

Pagina 15

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 22 of 28CapacitanceTested initially and after any design or p

Pagina 16

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 23 of 28Switching CharacteristicsOver the operating range[22,

Pagina 17

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 24 of 28Switching WaveformsRead/Write/Deselect SequenceFigure

Pagina 18

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 25 of 28Ordering Information Not all of the speed, package an

Pagina 19

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 26 of 28300 CY7C1141V18-300BZC 51-85180 165-Ball Fine Pitch B

Pagina 20

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 27 of 28Package DiagramFigure 8. 165-Ball FBGA (13 x 15 x 1.4

Pagina 21

Document Number: 001-06583 Rev. *D Revised March 06, 2008 Page 28 of 28QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate

Pagina 22

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 3 of 28Logic Block Diagram (CY7C1143V18)Logic Block Diagram (

Pagina 23

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 4 of 28Pin ConfigurationsCY7C1141V18 (2M x 8)165-Ball FBGA (1

Pagina 24

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 5 of 28Pin Configurations (continued)CY7C1143V18 (1M x 18)165

Pagina 25

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 6 of 28Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input

Pagina 26

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 7 of 28CQEcho Clock Synchronous Echo Clock Outputs. This is a

Pagina 27

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 8 of 28Functional OverviewThe CY7C1141V18, CY7C1156V18, CY7C1

Pagina 28

CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18Document Number: 001-06583 Rev. *D Page 9 of 28Depth ExpansionThe CY7C1143V18 has a Port Select input

Modelos relacionados CY7C1141V18 | CY7C1156V18 | CY7C1145V18 |

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Modelos relacionados CY7C1141V18 | CY7C1156V18 | CY7C1145V18 |

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