Cypress CY7C138 Manual de usuario

CY7C138, CY7C1394K x 8/9 Dual-Port Static RAMwith Sem, Int, BusyCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 40

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 10 of 17Figure 11. Write Timing with Busy Input (M/S=LOW)Notes27. I/O0R = I/O0L = LOW (request se

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 11 of 17Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)[30]Note30. If tPS is violated,

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 12 of 17Figure 14. Interrupt Timing DiagramsNotes31. tHA depends on which enable pin (CEL or R/WL

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 13 of 17ArchitectureThe CY7C138/9 consists of an array of 4K words of 8/9 bits eachof dual-port RA

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 14 of 17Table 3. Non-Contending Read/WriteInputs OutputsOperationCE R/W OE SEM I/O0-7/8H X X H Hi

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 15 of 17Figure 15. Typical DC and AC Characteristics1.41.00.44.0 4.5 5.0 5.5 6.0–55 25 1251.21.01

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 16 of 17Ordering Information4K x8 Dual-Port SRAMSpeed(ns)Ordering CodePackageNamePackage TypeOpera

Document #: 38-06037 Rev. *D Revised March 12, 2009 Page 17 of 17All products and company names mentioned in this document may be the trademarks of t

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 2 of 17Pin ConfigurationsFigure 1. 68-Pin PLCC (Top View)\Table 1. Pin DefinitionsLeft Port Righ

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 3 of 17Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These use

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 4 of 17Electrical Characteristics Over the Operating Range (continued)Parameter Description Test C

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 5 of 17Figure 2. AC Test Loads and Waveforms3.0VGND90%90%10%<3ns< 3 ns10%ALL INPUT PULSES(a

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 6 of 17tHDData Hold From Write End 0 0 0 0 nstHZWE[11,12]R/W LOW to High Z 10 15 20 25 nstLZWE[11,

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 7 of 17Figure 5. Read Timing with Port-to-Port Delay (M/S = L)[20, 21]Figure 6. Write Cycle No.

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 8 of 17Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)[22, 24, 25]Figure 8.

CY7C138, CY7C139Document #: 38-06037 Rev. *D Page 9 of 17Figure 9. Timing Diagram of Semaphore Contention[27, 28, 29]Figure 10. Timing Diagram of