Cypress CY62128EV30 Manual de usuario Pagina 11

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CubeSat Kit PPM B1 Rev. A
© Pumpkin, Inc. 2003-2009
11
of
14
August 2009 – document Rev. B
PPM PIN DESCRIPTIONS – I2C Bus
Name Pin I/O CSKB Description
SDA_SYS
H1.73 I/O
I2C data. To/from P0.6 (U1.56). Part of the I2C interface.
P0.6 is normally configured as an I2C data input/output. Can
also be used as general-purpose I/O.
SCL_SYS
H1.75 O
I2C clock. From P0.7 (U1.55). Part of the I2C interface.
P0.7 is normally configured as an I2C clock output. Can also
be used as general-purpose I/O.
PPM PIN DESCRIPTIONS – User-defined
Name Pin I/O CSKB Description
USER0
H1.77 I/O
Not connected.
USER1
H1.79 I/O
Not connected.
USER2
H1.81 I/O
Not connected.
USER3
H1.83 I/O
Not connected.
USER4
H1.85 I/O
Not connected.
USER5
H1.87 I/O
Not connected.
USER6
H1.89 I/O
Not connected.
USER7
H1.91 I/O
Not connected.
USER8
H1.93 I/O
Not connected.
USER9
H1.95 I/O
Not connected.
USER10
H1.97 I/O
Not connected.
USER11
H1.99 I/O
Not connected.
XRAM INTERFACE
PPM B1 uses the C8051's External Memory Interface (EMIF) to provide an external 1Mbit (128Kx8)
SRAM functioning as high-speed XRAM via a Cypress CY62128EV30 (U6).
6
A multiplexed interface is
implemented via U5 (SN74LVC373A) and U6. The 1Mbit SRAM is split into two selectable 64Kx8 pages.
To use the EMIF, it must be configured to appear on the upper GPIO ports P4-P7, –MEMBUS must be
active, and the desired bank must be selected via MEMBANK. Once configured,
7
the XRAM is accessed
via the MOVX instruction, etc. The pin assignments associated with this interface are listed below.
PIN DESCRIPTIONS – XRAM Interface
Name I/O Description
-MEMBUS
O
Memory Bus Enable. From P5.6 (U1.82). To U5's –OE pin and U6's –CE1 pin.
When disabled (i.e., -MEMBUS is high), XRAM is not available, and is in its
lowest-power state. When enabled, XRAM is available for full-speed operations.
MEMBANK
O
Bank select. From P5.7 (U1.81). To U6's A16 pin. Selects between lower and
upper 64Kx8 XRAM bank.
ALE
O
Address Latch Enable. From P4.5/ALE (U1.93). Part of U1's EMIF on P4-P7.
Latches the low-order bits of the multiplexed address EMIF address bus.
-RD
O
Read strobe. From P4.6/-RD (U1.92). Part of U1's EMIF on P4-P7. To U6's –OE
pin.
-WR
O
Write strobe. From P4.7/-WR (U1.91). Part of U1's EMIF on P4-P7. To U6's –WE
pin.
A[15..8]M
O
Multiplexed (upper) address bits. From P6[7..0] (U1.[80..73]). Part of U1's EMIF
on P4-P7. High-order address bits presented directly to U6's A[15..8].
AD[7..0]
I/O
Multiplexed (lower) address and data bits. To/from P7[7..0] (U1.[72..65]). Part of
U1's EMIF on P4-P7. Low-order address bits presented directly to latch U5's
D[7..0], and data bits read back from U6's IO[7..0].
6
Refer to the Cypress Semiconductor CY62128EV30 datasheet for more information.
7
Wait states must be properly configured in U1 prior to accessing the XRAM.
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