Cypress CY14B101LA Manual de usuario descargar pdf (Pagina 10)

PRELIMINARY

CY14B101LA, CY14B101NA

Document #: 001-42879 Rev. *B Page 10 of 25

Note

21. CE

or WE must be > V

during address transitions.

Figure 7. SRAM Read Cycle #2: CE and OE Controlled

[3, 15, 19]

Figure 8. SRAM Write Cycle #1: WE Controlled

[3, 18, 19, 21]

Address ValidAddress

Data Output

Output Data Valid

Standby

Active

High Impedance

BHE, BLE

HZCE

ACE

LZCE

DOE

LZOE

DBE

LZBE

HZBE

HZOE

Data Output

Data Input

Input Data Valid

High Impedance

Address ValidAddress

Previous Data

SCE

PWE

HZWE

LZWE

BHE, BLE

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Cypress CY14B101LA Manual de usuario Pagina 10