Cypress CY62167EV18 Manual de usuario descargar pdf (Pagina 16)

US

8,121,078

B2

11

Yanjun

Hu,

et

al.

entitled

“An

Ef?cient

Joint

Dynamic

Detec

tion

Technique

for

Wireless

Transmission

of

JPEG2000

Encoded

Images.”

The

CPU

110

also

includes

an

audio

compression

engine

118.

Memory

contained

in

the

CPU

110

can

store

both

com

pressed

and

uncompressed

video,

as

well

as

compressed

and

uncompressed

audio.

Under

low

battery

or

poor

data

radio

channel

bandwidth

conditions,

a

relatively

large

amount

of

energy

can

be

saved

by

disabling

the

bulk

high-bandwidth

radio

104

and

not

transferring

the

image,

audio

or

other

data

to

the

base

station

160.

In

this

mode,

the

?ash

memory

114

can

be

used

to

hold

a

signi?cant

amount

of

data

up

to

many

hours

until

the data

is

retrieved.

In

conditions

where

the radio

transmissions

are

interrupted

or

jammed;

for

example,

by

an

intruder,

an

alarm

can

be

initiated

silently

from

the

base

station

160

to

the

external

network

or

can

be

externally

indicated

by

visual

or

audible

transducers

activated

on

the

base

station

160

or

wireless

cam

era

100.

In

one

implementation,

alarms

can

be

triggered

if

data

transmissions

fail

for

a

speci?ed

amount

of

time.

This

failure

in

data

transmission

can be

caused

by

an

intentional

jamming

by

an

intruder

or

by

a

failure

to

establish

a

trans

mission

link.

In

such

situation,

the

wireless

camera

100 can

store

images

and/

or

audio

data

in

a storage

element,

such

as

a

?ash

memory

114,

for

transmission

or

retrieval

at

a

later

time.

Data

retrieval

at

a

later

time

can

be

achieved

by

manually

removing

the

camera

100

or

storage

element

from

the

camera

100

and

connecting

to

a

Windows,

Linux

or

Macintosh

based

computer

via a

Universal

Serial

Bus

(U

SB).

The

storage

unit

can

appear

to

the

computer

to

be

a

standard

mass

storage

device

with

?les

of

the

captured

data.

In

another

implemen

tation,

when

there

is

a

failure

in

data

transmission,

the

system

can

use

an

alternative

wireless

connection

to

transfer

data,

for

example,

such

as

operating

on

a

different

frequency,

using

different

modulation

methods,

or

by

increasing

the

output

power

of

the

wireless

transmitter.

The

compression

engines

116 and

118 can

operate

on

captured

data

output

from

the

sensors

connected

to

the

CPU

110.

Alternatively,

the

compression

engines

116

and 118

can

operate

on

captured

data

temporarily

stored

inside

the

?ash

memory

114.

In

this

manner,

the

compression

and

capture

processes

can

operate

on

independent

cycles.

This

indepen

dence

can

also

help

maximize

energy

e?iciency.

For

example,

the

image

capture

may

be

occurring

5

times

a

second,

but

the

compression

engine

may

operate

at

very

high

speed

on

mul

tiple

images

every

3

seconds.

In

this

fashion,

the

energy

requirements

of

starting

up

the

compression

engines

116

and

118

can

be

amortized

over

a

large

amount

of

data.

In

one

example,

the

?ash

memory

114

can

hold

approximately

15

uncompressed

images

before

the

compression

engine

is

acti

vated.

In

some

implementations,

most

or

all

components

of

the

compression

engines

116 and

118

can be

integrated

into

the

microcontroller

112

and

peripheral

blocks.

In

this

way,

the

compression

can be

achieved

in

the

microcontroller

112

using

a

hybrid

software

and

hardware

acceleration

for

computa

tional

intensive

processing.

Other

alternatives

for

the

com

pression

engines

116

and

118

can

include

a separate

applica

tion

speci?c

integrated

circuit

(ASIC)

or a

?eld

programmable

gate array

(FPGA).

An

example

FPGA

can

be

one

based

on

?ash

technology

such

as

Actel

Corporation’s

Fusion

product

line,

where

the

“instant

on”

allows

for

rapid

start-up

capabilities

reducing

energy

wastage

during

the

cycling

process.

Alternatively,

the

image

capturing

module

120

can

have

an

integrated

compression

engine

and

output

compressed

data

directly to

the

CPU

110.

20

25

30

35

40

45

50

55

60

65

12

The

CPU

110

can

also

perform

the

burst

transmission

store/

control

MAC

process

needed

to

transfer

the

data

trans

mission

from

the

bulk

high-bandwidth

radio

104.

The

high

bandwidth

radio

104 can

be

power

cycled

based

on

the

physi

cal

layer

characteristics

of

the radio

and

sustained

bandwidth

needed

to

maintain

certain

?delity

of

the

images

and

audio

transmitted.

The

power

cycling

of

the

high-bandwidth

radio

104

is

further

described

in

more

detail

below.

In

general

operation,

the

microcontroller

112

canbe

started

from

a

deep

power

save

mode

by

the

clock

111,

which

can

be,

e.g.,

an

ultra

low

power

real

time

clock.

The

timing

of

this

can

vary

depending

on

the

aggregate

needs

of

the

multiple

pro

cesses

as

they

cycle.

Therefore,

once

powered

up

the

software

can be

used

to

initiate

or

manage

one

or

more

processes

including

image

capture,

data

transmission,

and

image

com

pression.

In

some

instances,

the

clock

111

can

be

replaced

by

a

microcontroller

with

integrated

low

power

real

time

clock

capability.

An

example

of

such

a

microcontroller

is

the

Texas

Instruments

MSP43O

family

of

products.

In

one

implementation,

most

or

all

of

the

timing

required

for

the

wireless

camera

100

can

originate

from

the

base

sta

tion

160

and

be

communicated

to

the

wireless

camera

100

through

a

secondary

receiver

(e.g.,

the

low-bandwidth

radio

106),

as

will

be

described

in

more

detail

below.

This

con?gu

ration

can

act as

an

alternative

to

using

the

clock

111

described

above,

and

allow

for

more

of

the

processing

com

plexity

to

reside

in

the

base

station

160.

Additionally,

the

wireless

camera

100

can be

simpli?ed,

cheaper,

and

more

robust.

Furthermore,

the

wireless

camera

100

can

consume

less

power

because

very

little

timing

processing

would

be

needed

in

the

wireless

camera

100.

In

this

way,

the

wireless

camera

100

can

act as

a

“slave”

unit

and

the

commands

for

the

processing

elements

described

below

can

be

issued

directly

from

the

base

station

160.

In

general,

all

the

processing

can

operate

on

cycles

inde

pendent

of each

other

to

maintain

maximum

e?iciency.

Memory

can be

used

to

buffer data

between

processes

to

allow

for

this.

This

buffering

memory

can

be

used

to

ensure

that

data

overrun

or

data

under-run

does

not

occur

during

operation.

This

buffering

memory

can

be

designed

to

operate

at

an

extremely

low

power

during

non

active

or

retention

modes

that

can

occur

between

processing

cycles.

This buff

ering

memory

can

be

distributed

between

some

or

all

of

various

integrated

circuits

that

constitute

the

wireless

camera

100.

Alternatively,

a

portion

of

the

buffering

can be

concen

trated

in

specialized

memory

components.An

example

of

this

kind

of

memory

component

can

be

the

Cypress

Semiconduc

tor

Corporation’s

16

Mbit

SRAM

memory

product

CY62167EV18.

As

shown

in

FIG.

1,

a

number

of

modules

can

interface

to

the

CPU

110.

The

image

capturing

module

120

can

include

a

low

power

imager

such

as

a

CMOS

based

sensor.

Altema

tively,

a

CCD

can

be

used,

but

typically

these

devices

use

more

energy

than

CMOS

devices

for

a

given

frame

rate,

resolution

and

?delity.

The

circuitry

supporting

the

sensor

can

include

memory

to

temporarily

hold

uncompressed

images.

In

one

implementation,

image

capturing

module

120

can

also

include

an

image

compression

engine

and

memory

that stores

both

compressed

and

uncompressed

images.

In

some

CMOS

imagers,

so

called

“active

pixel”

technology

can

be

used

to

allow

the

imager

to

power

up

and

respond

very

rapidly

to

an

image

exposure

command

and

then automati

cally

power

down.

In

some

implementations,

the

imager

can

have

a

number

of

active

circuits

per

pixel

(such

as

analog

to

digital

converters)

to

enable

for

rapid

operation

for

brief

periods

of

time,

fol

lowed

by

very

low

power

standby

energy

consumption.

This

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