Cypress CY7C65113C Manual de usuario Pagina 1

USB Hub with MicrocontrollerCY7C65113CCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 38-0

CY7C65113CDocument #: 38-08002 Rev. *D Page 10 of 494.3 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for more details. Note that

CY7C65113CDocument #: 38-08002 Rev. *D Page 11 of 495.0 Programming Model5.1 14-bit Program CounterThe 14-bit Program Counter (PC) allows access to

CY7C65113CDocument #: 38-08002 Rev. *D Page 12 of 495.1.1 Program Memory Organization Note that the upper 32 bytes of the 8K PROM are reserved. Ther

CY7C65113CDocument #: 38-08002 Rev. *D Page 13 of 495.2 8-bit Accumulator (A)The accumulator is the general-purpose register for the microcontroller

CY7C65113CDocument #: 38-08002 Rev. *D Page 14 of 495.5 8-bit Data Stack Pointer (DSP)The Data Stack Pointer (DSP) supports PUSH and POP instruction

CY7C65113CDocument #: 38-08002 Rev. *D Page 15 of 496.0 ClockingThe XTALIN and XTALOUT are the clock pins to the microcontroller. The user can conn

CY7C65113CDocument #: 38-08002 Rev. *D Page 16 of 497.2 Watchdog ResetThe WDR occurs when the internal Watchdog Timer rolls over. Writing any value

CY7C65113CDocument #: 38-08002 Rev. *D Page 17 of 499.0 General-purpose I/O PortsThere are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware inte

CY7C65113CDocument #: 38-08002 Rev. *D Page 18 of 499.1 GPIO Configuration PortEvery GPIO port can be programmed as inputs with internal pull-ups, o

CY7C65113CDocument #: 38-08002 Rev. *D Page 19 of 49 Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO

CY7C65113CDocument #: 38-08002 Rev. *D Page 2 of 49TABLE OF CONTENTS1.0 FEATURES ...

CY7C65113CDocument #: 38-08002 Rev. *D Page 20 of 49Bit [7:0]: Timer lower eight bits. Bit [3:0]: Timer higher nibbleBit [7:4]: Reserved.11.0 I2C

CY7C65113CDocument #: 38-08002 Rev. *D Page 21 of 4912.0 I2C-compatible ControllerThe I2C-compatible block provides a versatile two-wire communicat

CY7C65113CDocument #: 38-08002 Rev. *D Page 22 of 49Bit 7 : MSTR ModeSetting this bit to 1 causes the I2C-compatible block to initiate a master mode

CY7C65113CDocument #: 38-08002 Rev. *D Page 23 of 4913.0 Processor Status and Control Register Bit 0: RunThis bit is manipulated by the HALT instru

CY7C65113CDocument #: 38-08002 Rev. *D Page 24 of 4914.0 InterruptsInterrupts are generated by GPIO pins, internal timers, I2C-compatible operation

CY7C65113CDocument #: 38-08002 Rev. *D Page 25 of 49During a reset, the contents of the Global Interrupt Enable Register and USB End Point Interrupt

CY7C65113CDocument #: 38-08002 Rev. *D Page 26 of 49Although Reset is not an interrupt, the first instruction executed after a reset is at PROM addr

CY7C65113CDocument #: 38-08002 Rev. *D Page 27 of 4914.5 USB Endpoint InterruptsThere are five USB endpoint interrupts, one per endpoint. A USB endp

CY7C65113CDocument #: 38-08002 Rev. *D Page 28 of 493. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if th

CY7C65113CDocument #: 38-08002 Rev. *D Page 29 of 496. The host sends a request for the Device descriptor using the new USB address.7. Firmware deco

CY7C65113CDocument #: 38-08002 Rev. *D Page 3 of 4916.0 USB HUB ...

CY7C65113CDocument #: 38-08002 Rev. *D Page 30 of 49Bit [0..3] : Port x Speed (where x = 1..4).Set to 1 if the device plugged in to Port x is Low Sp

CY7C65113CDocument #: 38-08002 Rev. *D Page 31 of 49The downstream USB ports are designed for connection of USB devices, but can also serve as outpu

CY7C65113CDocument #: 38-08002 Rev. *D Page 32 of 49. Bit [0..3] : Port x Diff Data (where x = 1..4).Set to 1 if D+ > D- (forced differential 1,

CY7C65113CDocument #: 38-08002 Rev. *D Page 33 of 49 Bit [0..3] : Resume x (where x = 1..4).When set to 1 Port x requesting to be resumed (set by ha

CY7C65113CDocument #: 38-08002 Rev. *D Page 34 of 49Bit 3: Bus Activity.This is a “sticky” bit that indicates if any non-idle USB event has occurred

CY7C65113CDocument #: 38-08002 Rev. *D Page 35 of 49When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. Thi

CY7C65113CDocument #: 38-08002 Rev. *D Page 36 of 49Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE

CY7C65113CDocument #: 38-08002 Rev. *D Page 37 of 49Bit 6: Data Valid.This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loa

CY7C65113CDocument #: 38-08002 Rev. *D Page 38 of 49 ACK1. IN TokenHOSTDEVICESYNCINADDRCRC5ENDPSYNCDATA1/0CRC16SYNCDataToken Packet Data PacketHand

CY7C65113CDocument #: 38-08002 Rev. *D Page 39 of 4918.0 USB Mode TablesModeThis lists the mnemonic given to the different modes that can be set in

CY7C65113CDocument #: 38-08002 Rev. *D Page 4 of 49Figure 16-5. Hub Ports Force Low Register ...

CY7C65113CDocument #: 38-08002 Rev. *D Page 40 of 49CommentsSome Mode Bits are automatically changed by the SIE in response to certain USB transacti

CY7C65113CDocument #: 38-08002 Rev. *D Page 41 of 49. Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2 for the decode

CY7C65113CDocument #: 38-08002 Rev. *D Page 42 of 490 0 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes0 0 1 0 Out > 10 UC x

CY7C65113CDocument #: 38-08002 Rev. *D Page 43 of 49 19.0 Register Summary Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R

CY7C65113CDocument #: 38-08002 Rev. *D Page 44 of 49HUB PORT CONTROL, STATUS, SUSPEND RESUME, SE0, FORCE LOW 0x48 Hub Port Connect Status Reserved R

CY7C65113CDocument #: 38-08002 Rev. *D Page 45 of 4920.0 Sample Schematic21.0 Absolute Maximum RatingsStorage Temperature ...

CY7C65113CDocument #: 38-08002 Rev. *D Page 46 of 4922.0 Electrical CharacteristicsfOSC = 6 MHz; Operating Temperature = 0 to 70°C, VCC = 4.0V to 5

CY7C65113CDocument #: 38-08002 Rev. *D Page 47 of 49 23.0 Switching Characteristics (fOSC = 6.0 MHz) Parameter Description Min. Max. UnitClock Sou

CY7C65113CDocument #: 38-08002 Rev. *D Page 48 of 49© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to chang

CY7C65113CDocument #: 38-08002 Rev. *D Page 49 of 49Document History Page Document Title: CY7C65113C USB Hub with MicrocontrollerDocument Number: 38

CY7C65113CDocument #: 38-08002 Rev. *D Page 5 of 491.0 Features• Full Speed USB hub with an integrated microcontroller• 8-bit USB optimized microco

CY7C65113CDocument #: 38-08002 Rev. *D Page 6 of 492.0 Functional OverviewThe CY7C65113C device is a one-time programmable 8-bit microcontroller wi

CY7C65113CDocument #: 38-08002 Rev. *D Page 7 of 49 Logic Block DiagramInterruptControllerPROM12-bitTimerResetWatchdogTimerRepeaterPower-onSCLKI2C c

CY7C65113CDocument #: 38-08002 Rev. *D Page 8 of 494.0 Product Summary Tables4.1 Pin Assignments 3.0 Pin ConfigurationsTable 4-1. Pin Assignments

CY7C65113CDocument #: 38-08002 Rev. *D Page 9 of 494.2 I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, I