Cypress Perform CY7C136A Manual de usuario descargar pdf (Pagina 8)

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Document #: 38-06031 Rev. *E Page 8 of 15

Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)

Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)

[12, 20]

Switching Waveforms (continued)

BHA

BDD

VALID

DDD

WDD

ADDRESS MATCH

R/W

ADDRESS

INR

ADDRESS

BUSY

DOUT

BLA

PWE

VALID

DATA VALID

HIGH IMPEDANCE

SCE

PWE

HZOE

R/W

ADDRESS

OUT

DATA

Note

20. If OE

is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t

PWE

or t

HZWE

+ t

to allow the data I/O pins to enter high impedance

and for data to be placed on the bus for the required t

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Cypress Perform CY7C136A Manual de usuario Pagina 8