Cypress CY7C1354CV25 Manual de usuario descargar pdf

9-Mbit (256K x 36/512K x 18)

elined SRAM with NoBL™ Architecture

CY7C1354CV25

CY7C1356CV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05537 Rev. *H Revised September 14, 2006

Features

• Pin-compatible with and functionally equivalent to

ZBT™

• Supports 250-MHz bus operations with zero wait states

• Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply (V

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

[1]

The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354CV25 and

CY7C1356CV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354CV25

and CY7C1356CV25 are pin-compatible with and functionally

equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN

) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354CV25 and BW

–BW

for

CY7C1356CV25) and a Write Enable (WE

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram–CY7C1354CV25 (256K x 36)

[+] Feedback

1 2 3 4 5 6 ... 27 28

Indice de contenidos

Pagina 1 - 9-Mbit (256K x 36/512K x 18)

9-Mbit (256K x 36/512K x 18)Pipelined SRAM with NoBL™ ArchitectureCY7C1354CV25CY7C1356CV25Cypress Semiconductor Corporation • 198 Champion Court • San

Pagina 2 - Selection Guide

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 10 of 28IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1354CV25/CY7C1356CV25 incorporates a

Pagina 3 - (512K × 18)

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 11 of 28It is also loaded with the IDCODE instruction if the controller isplaced in a reset

Pagina 4

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 12 of 28TAP TimingTAP AC Switching Characteristics Over the Operating Range[11, 12]Parameter

Pagina 5 - 165-Ball FBGA Pinout

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 13 of 282.5V TAP AC Test ConditionsInput pulse levels ...

Pagina 6

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 14 of 28Boundary Scan Exit Order (256K × 36) Bit # 119-ball ID 165-ball ID1K4 B62H4 B73M4 A7

Pagina 7

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 15 of 28Boundary Scan Exit Order (512K × 18) Bit # 119-ball ID 165-ball ID1K4 B62H4 B73M4 A7

Pagina 8

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 16 of 28Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, n

Pagina 9

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 17 of 28Capacitance[16]Parameter Description Test Conditions100 TQFP Max.119 BGA Max.165 FBG

Pagina 10 - [+] Feedback

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 18 of 28Switching Characteristics Over the Operating Range[18, 19]Parameter Description–250

Pagina 11

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 19 of 28Switching WaveformsRead/Write Timing[23, 24, 25]Notes: 23. For this waveform ZZ is t

Pagina 12 - TAP Timing

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 2 of 28 A0, A1, ACMODEBWaBWbWECE1CE2CE3OEREAD LOGICDQsDQPaDQPbDATASTEERINGOUTPUTBUFFERSMEMOR

Pagina 13

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 20 of 28NOP, STALL and DESELECT CYCLES[23, 24, 26]Note: 26. The IGNORE CLOCK EDGE or STALL c

Pagina 14

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 21 of 28ZZ Mode Timing[27, 28]Notes: 27. Device must be deselected when entering ZZ mode. Se

Pagina 15

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 22 of 28Ordering InformationNot all of the speed, package and temperature ranges are availab

Pagina 16 - Operating Range

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 23 of 28200 CY7C1354CV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead

Pagina 17

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 24 of 28250 CY7C1354CV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead

Pagina 18

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 25 of 28Package DiagramsNOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUD

Pagina 19 - Switching Waveforms

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 26 of 28Package Diagrams (continued)1.2720.322165437LEABDCHGFKJUPNMTR12.0019.5030° TYP.2.40

Pagina 20 - 45678910

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 27 of 28© Cypress Semiconductor Corporation, 2006. The information contained herein is subje

Pagina 21

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 28 of 28Document History PageDocument Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512

Pagina 22

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 3 of 28Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSNC VDDDQaD

Pagina 23

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 4 of 28Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNC/576MNC/1GDQcDQdDQcDQd

Pagina 24

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 5 of 28Pin Configurations (continued)234 5671ABCDEFGHJKLMNPRTDONC/576MNC/1GDQPcDQcDQPdNCDQdA

Pagina 25

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 6 of 28Pin Definitions Pin Name I/O Type Pin DescriptionA0A1AInput-SynchronousAddress Inputs

Pagina 26

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 7 of 28Functional OverviewThe CY7C1354CV25 and CY7C1356CV25 aresynchronous-pipelined Burst N

Pagina 27

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 8 of 28order to greatly simplify Read/Modify/Write sequences, whichcan be reduced to simple

Pagina 28

CY7C1354CV25CY7C1356CV25Document #: 38-05537 Rev. *H Page 9 of 28NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-StateWRITE ABORT (Continue B

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