Document Number: 001-52040 Rev. *C Page 17 of 24
Figure 14. Interrupt Block Diagram
Interrupt Register
Watchdog Interrupt Enable (WIE). When set to ‘1’, the watchdog
timer drives the INT pin when a watchdog time-out occurs. When
WIE is set to ‘0’, the watchdog time-out only sets the WDF flag
bit.
Alarm Interrupt Enable (AIE). When set to ‘1’, the INT pin is
driven when an alarm match occurs. When set to ‘0’, the alarm
match only sets the AF flag bit.
Power Fail Interrupt Enable (PFE). When set to ‘1’, the INT pin
is driven by a power fail signal from the power monitor. When set
to ‘0’, only the PF flag is set.
High/Low (H/L). When set to ‘1’, the INT pin is active high and
the driver mode is push-pull. The INT pin can drive high only
when V
CC
>V
SWITCH
. When set to ‘0’, the INT pin is active low
and the drive mode is open-drain. The active low (open drain)
output is maintained even when power is lost.
Pulse/Level (P/L). When set to ‘1’, the INT pin is driven for
approximately 200 ms when the interrupt occurs. The pulse is
reset when the Flags register is read. When P/L is set to ‘0’, the
INT pin is driven high or low (determined by H/L) until the Flags
register is read.
The Interrupt register is loaded with the default value 00h at the
factory. Configure the Interrupt register to the desired value for
the desired mode of operation. Once configured, the value is
retained during power failures.
Flags Register
The Flags register has three flag bits: WDF, AF, and PF. These
flags are set by the watchdog time-out, alarm match, or power
fail monitor respectively. The processor can either poll this
register or enable the interrupts to be informed when a flag is set.
The flags are automatically reset when the register is read.
The Flags register is automatically loaded with the value 00h on
power up (with the exception of the OSCF bit).
Watchdog
Timer
Power
Monitor
Clock
Alarm
PF
PFE
VINT
AIE
AF
P/L
H/L
Pin
Driver
INT
V
CC
WIE
WDF
V
SS
Not Recommended for New Designs
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